1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a method for predicting the performance of a microelectronic device based on electrical parameter test data using a computer model.
2. Description of the Related Art
Fabrication of microelectronic integrated circuit chips such as microprocessors, memories, etc. is extremely complex and involves a large number of process steps and variables. A defect in any of the process steps can result in the production of an entire lot of unusable chips. It is therefore necessary to monitor the quality of the chips throughout the fabrication process and detect any defects as early as possible so that time will not be wasted performing additional fabrication steps on defective circuits.
The integrated circuit fabrication process comprises performing numerous process steps including deposition, oxidation, etching, ion implantation, photolithographic definition, metallization, etc. to form a plurality of integrated circuit dies on semiconductor wafers. After these steps are completed, the wafers are subjected to Wafer Electrical Testing (WET) to obtain electrical circuit parameters or parametric test values.
A large number of tests are typically performed to obtain parameters. These values include, for example, V.sub.TN (threshold voltage of NMOS field effect transistors), I.sub.DN (source/drain current of NMOS transistors in the linear and saturation regions), V.sub.TP (threshold voltage of PMOS transistors), I.sub.DP (source/drain current of PMOS transistors), metal 1/2/3 sheet rho (transconductance of 1st, 2nd and 3rd metal layers), etc. It is not uncommon for WET testing to produce 150 to 300 or more parameters.
The wafers are then sorted based on the results of the WET testing. If certain parameters are out of tolerance for any of the dies on a wafer, at least the defective dies and in extreme cases entire wafers are rejected.
The next step of the process is assembly, in which the individual dies are cut away from the wafers and probed, passing dies will be assembled into individual packages which are provided with pins or other means for electrically interconnecting the microelectronic devices of the dies to external circuitry. The assembled chips are then subjected to package testing to determine if the interconnections have been made properly.
Finally, the finished integrated circuit chips are subjected to functional and performance testing. The former tests including applying electrical test signals or test vector sets to inputs of the chips and reading data appearing at the outputs to detect any functional defects in the chips. The latter tests include testing the operating speed and other characteristics of the chips.
Regarding operating speed, any chips which perform below a minimum criteria, for example 80 Mhz, will be rejected. Chips having speeds above the minimum value will be graded for sale at different quality levels and prices. For example, quality levels A, B and C may correspond to operating speeds of above 100 Mhz, 90 to 100 Mhz and 80 to 90 Mhz respectively.
It is desirable to predict performance parameters including the operating speeds and possible reject conditions in a production lot of chips as early as possible, and using WET test data after fabrication is a logical step to check overall process and functionality of devices. It seems to be a common choice for people to use WET data to predict device preformance. Since there is a large number of parameters and complex interaction between parameters, this is extremely difficult to perform with a high degree of accuracy. Conventional evaluation of WET parameters and device performance is as much an art as a science, and is subjectively based on intuition resulting from years of extensive experience in semiconductor fabrication.
Although attempts have been made to automate evaluation of WET parameters to provide objective criterion, such expedients have been limited to a small number, for example three, key parameters and have provided limited results of questionable reliability.
It is also desirable to detect process conditions which would result in less than satisfactory performance during the lengthy fabrication process and provide adjustments which improve the quality of the products. For example, a few test wafers of a production lot can be tested or measured against process specs, and the test results used to fine-tune the fabrication of the remainder of the lot.